Non-volatile memory cells are known in the art, as are nitride read only memory (NROM) cells, which store two bits per cell. A memory chip typically includes an array of these cells, with each bit of each cell being individually accessible.
FIGS. 1A and 1B, to which reference is now made, illustrate two exemplary, prior art memory chips, which includes the array, labeled 10, of NROM cells 12, an X decoder 14, a Y decoder 16 and a Y multiplexer (Y-MUX) 18. The array of FIG. 1A is a segmented virtual ground array and is described in U.S. Pat. No. 6,633,496, assigned to the common assignee of the present invention and the array of FIG. 1B is based on the segmented array structure as described in U.S. Pat. No. 6,614,692, assigned to the common assignee of the present invention.
In both embodiments, array 10 comprises word lines WL(i) and local bit lines BLj to which the NROM cells 12 are connected and through which NROM cells 12 are accessed. Each NROM cell, such as cells 12A and 12B (FIG. 1A), comprises a gate terminal G, and two diffusions F acting as the source or drain of the cell. Each word line WL(i) connects together a row of NROM cells 12 by connecting their gates G together. Moreover, the diffusions F of each two neighboring cells of a row are connected together. Each local bit line BLj connects together two columns of NROM cells 12, connecting together their diffusions F. Thus, bit line BL8 connects the diffusions F of cells 12A and 12B to the diffusions F of cells connected to other WL's but sharing the same column (like cells 12D and 12E). Array 10 also comprises global bit lines GBL(n) and select cells 20. Global bit lines GBL(n) are connected between Y-MUX 18 and select cells 20 and select cells 20 connect the global bit lines GBL(n) to local bit lines BLj.
In the embodiment of FIG. 1B, there are isolation areas 22 which electrically isolate one or more columns of cells 12 from its neighboring columns.
X decoder 14 activates a row of NROM cells 12 by activating an individual word line WL(i). Y decoder 16 decodes the Y address of a bit to be accessed and instructs Y-MUX 18 to select the global bit lines GBL(n) connectable to the local bit lines BLj of the cell housing the bit to be accessed. X decoder 14 also activates the SELECT lines associated with the select cells 20 needed to connect the selected global bit line GBL(n) to the desired local bit line BLj.
For example, to program a bit, all the global bit lines GBL are initially discharged and floating. To program a bit in cell 12C, X decoder 14 may first activate word line WL(i), to activate the gate of cell 12C. As word line WL(i) rises to its programming voltage level, X-decoder 14 may select the bit line access path by activating select lines SEL-5 and SEL-4 to activate select cells 20A and 20B, respectively. Y-MUX 18 may drive GBL(N) and GBL(N+1) to GND and may leave all the other global bit lines floating.
In order to apply the programming pulse that will program the cell's bit (the right side charge storage area as in FIG. 1A or the left side storage area as in FIG. 1B), Y-MUX 18 drives global bit line GBL(N) to a high voltage (HV), about 4-6V, global bit line GBL(N+1) to GND (0V) or another close to GND potential, and all other global bit lines typically remain floating.
Select cell 20A passes the high voltage of global bit line GBL(N) to local bit line BL12 and thus, to the diffusion F acting as a source of cell 12C. Select cell 20B passes the ground voltage of global bit line GBL(N+1) to local bit line BL13 and thus, to the diffusion F acting as the drain of cell 12C. The dotted line indicates the flow of current from Y-MUX 18, through cell 12C and back to Y-MUX 18. The programming pulse ends by driving global bit line GBL(N) low.
Reference is now made to FIG. 2, which illustrates the activation timing for programming a multiplicity of cells. This programming method is discussed in U.S. Publication 2003-0145176-A1, which application is co-owned by the common assignee of the present invention.
Initially (graph (a)), the selected word line WL(i) is driven to a high voltage (e.g. 9V). At about the same time, or shortly thereafter, the relevant select lines SEL-x are also activated (graph (b)) to define the conducting path to the cell to be accessed. In graph (c), a GND or close to GND potential is driven to the drain and source terminals of the NROM cell to be accessed. Finally, as shown in graph (d), a high voltage pulse is applied to the global bit line (GBL) to be connected to the cell's drain terminal, to provide a programming pulse. The programming pulse (PGM'ing Pulse) is followed by a program verify operation (PGM Verify) (which requires different voltage levels at the NROM cell terminals).
When programming a large number of cells (e.g. in a 512B page write operation), programming pulses may be applied to all the cells on the selected word line WL(i) to be programmed before applying the program verify test. This is shown in graphs (b) and (d) by the multiple transitions. Reference is now made to FIG. 3, which schematically illustrates the flow of direct current IDC during a programming pulse. DC current IDC flows from a power supply 30, through a high voltage supply system 32 (which may include charge pumps, regulators, or boosters), along a first, long global bit line GBL(1), through cell 12 to be programmed, along a second long global bit line GBL(2), until it reaches a ground supply 34. Along this current path there are usually additional conducting transistors (not shown in FIG. 3) which serve as switches. The high voltage supply system 32 generates programming voltage levels (HV) which are significantly higher than the voltage level of power supply 30 (Vcc). The power efficiency (η) of the high voltage supply system is typically low (less than 50%) and therefore the current consumed from the power supply 30 (ICC,DC) is significantly larger than IDC. Specifically,ICC,DC=HV*IDC/VCC/η
The DC current IDC may be relatively large during programming, especially if many cells need to be programmed in parallel in order to achieve high programming rates. In addition, in the programming sequence shown in FIG. 2, each programming pulse charges and discharges the associated GBL. In high density memory devices, the parasitic capacitances CBL associated with the global bit lines may be relatively large. The larger the capacitance CBL is, the larger the dynamic current consumed from the high voltage supply system 32. In addition, in the sequence shown in FIG. 2, the capacitances CBL are charged and discharged many times during a programming operation. The dynamic current consumed from the high voltage supply system 32 is high, and the current consumed from the power supply 30 is even higher (due to the low efficiency of the high voltage supply system 32).
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.